1. Field of the Invention
The present invention relates generally to protection devices, and, more particularly, to protection devices for protecting integrated circuit devices from electrical transients, including electrostatic discharge (ESD) events.
2. Description of the Related Art
Integrated circuit devices have been subject to ever increasing susceptibility to damage from application of excessive voltages, for example, by electrostatic discharge (ESD) events. This susceptibility is due, in large part, to the ever decreasing gate oxide thicknesses which have resulted as very large scale integration (VLSI) circuit geometries continued to shrink. In particular, during an ESD event, charge is transferred between one or more pins of the integrated device and another conducting object in a time period that is typically less than one microsecond. As indicated above, this charge transfer can generate voltages that are large enough to break down insulating films (e.g., gate oxides) on the device or can dissipate sufficient energy to cause electrothermal failures in the device. Such failures include contact spiking, silicon melting, or metal interconnect melting.
Accordingly, there have been many attempts made in the prior art to protect semiconductor devices, with particular attention to the problem of protecting field effect transistor devices from such ESD events. FIG. 1 is representative of a common approach taken in the prior art to protect integrated circuit devices. An input/output circuit, including protection circuitry, is indicated generally at 10 and is provided for protecting an input buffer 12, and an output buffer 14, from ESD events occurring at input/output (I/O) pad 16. Circuit 10 includes a primary ESD protection circuit 18, a secondary ESD protection circuit 20, a core clamp 22, and ESD clamps 24, and 26.
In addition to the basic protection circuits, an integrated circuit device may have separate power supply buses for output drivers and internal circuits. Separate buses have the effect of reducing noise generated by the output drivers (because of large current transients) from appearing on the power supply buses provided for the internal circuits. The positive output power supply bus is indicated at V.sub.DDO, while the negative output power supply bus is denoted V.sub.SSO. The internal power supply buses are indicated at V.sub.SSI, and V.sub.DDI. These power supply buses may be shorted together on the die, or, on the package of the semiconductor device. In some cases, there may only be a single pair of power supplies, V.sub.SS and V.sub.DD, which are used for both output drivers and internal circuits.
Protection circuits, such as those found in structure 10, are usually connected to all I/O pads of an integrated circuit to safely dissipate the energy associated with ESD events. This energy dissipation prevents, generally, damage to all the internal circuitry, such as input buffer 12, or output buffer 14, that is connected to I/O pad 16. The double diode primary ESD circuit 18 includes diodes D.sub.1, and D.sub.2, and is connected between V.sub.DDO and V.sub.SSO, with input pad 16 being connected at a node common to diodes D.sub.1 and D.sub.2. The primary ESD circuit 18 carries the majority of the charge during an ESD event. In particular, diode D.sub.1 shunts ESD charge to the V.sub.SSI bus when the polarity is negative, while diode D.sub.2 shunts ESD charge to the V.sub.DDO bus when the polarity is positive. Secondary ESD protection circuit 20 includes a resistor R in series with a grounded gate FET clamp M.sub.O, which is operative to limit the voltage across the gate oxides of input buffer 12. The amount of charge that flows through secondary ESD protection circuit 20 is relatively small in comparison to the amount of charge flowing through primary ESD protection circuit 18. Core clamp 22 permits charge to be transferred between the internal power supply buses V.sub.DDI and V.sub.SSI during an ESD event. ESD clamps 24, and 26 are placed between each pair of V.sub.SS, and V.sub.DD supplies to allow charge to be transferred between the power supply buses during an ESD event.
A particularly significant problem encountered in the art relates generally to protecting output driver 14 from damage due to ESD events. Protection circuits similar to input protection circuits may not be employed, generally, at outputs because design constraints do not permit the use of a resistance between the output buffer and the interface pad. As shown in FIG. 1, output driver 14 includes an active p-channel pullup device 30, and an n-channel pulldown device 28 connected between V.sub.DDO and V.sub.SSO. The use of silicided source/drain diffusions have only exacerbated the ESD protection problem.
A better understanding of the problems existent in the prior art may be had by reference to FIG. 2. At the outset, it should be noted that a commonly employed architecture in the design of output driver 14 is the use of a plurality of individual pulldown n-channel field effect transistors (FETs) for pulldown device 28. That is, the device 28 shown schematically in FIG. 1 as a single transistor, is, as actually fabricated, a plurality of individual transistors 28.sub.1, 28.sub.2, . . . 28.sub.N, connected in parallel (i.e., gate electrodes tied; source electrodes tied; and drain electrodes tied). This arrangement is also known as a so-called "multi-finger" architecture, each FET being a "finger." Diode D.sub.2 is merged with the drain of p-channel pullup output driver FET 30, and can be connected to V.sub.DDO, since FET 30, and diode D.sub.2 are placed in an n-well in a p-type substrate, which is electrically isolated from other such n-wells connected to V.sub.DDI (this merged configuration is not shown). As mentioned above, isolation is required to maintain the internal power supply buses "clean" relative to the "dirty" output power supply buses.
FIG. 2 shows a portion of output driver 14 fabricated on a p-type conductivity substrate 32. Device 28 includes a plurality of n-channel FETs 28.sub.1, 28.sub.2, . . . 28.sub.N. FET 28.sub.1 includes a source region, such as n.sup.+ -type conductivity region 34.sub.1, a drain region, such as n.sup.+ -type conductivity region 36.sub.1, gate oxide 38.sub.1, and a gate electrode, such as polycrystalline silicon ("poly") gate electrode 40.sub.1. N-channel pulldown FET 28.sub.2 is identical. Diode D.sub.1 includes a p.sup.+ -type conductivity region 42 and is merged with drain 36 of n-channel pulldown FET 28; it must therefore be connected to power supply bus V.sub.SSI to avoid shorting it to the output power supply bus V.sub.SSO through p-type substrate 32. A layout view corresponding to this structure is shown in FIG. 3.
A major problem in the prior art is that n-channel pulldown device 28 can "snapback" and fail during a positive polarity ESD event with respect to V.sub.SS. The desired path for charge in this type of ESD event is through diode D.sub.2 to V.sub.DDO, and then through the power supply ESD protection structures (i.e., 22, 24, 26) to one of the V.sub.SS buses. However, if the voltage on pad 16 increases to a high enough value (i.e., a predetermined threshold value) during an ESD event, then the n.sup.+ drain region/p-substrate junction of pulldown device 28 will break down, and enter into a "snapback" mode. In "snapback" mode, device 28 operates as a parasitic lateral npn bipolar transistor with base current being supplied by holes generated by impact ionization near the drain region of the channel. As shown in FIG. 2, for pulldown FET 28.sub.1, a lateral npn bipolar transistor 44.sub.1 is formed during snapback. Once the pulldown FET 28.sub.1 snaps back, it has a low resistance and will conduct a significant portion of the ESD current. It is difficult to achieve acceptable ESD failure thresholds when the n-channel output device 28 snaps back due to nonuniformities of current flow.
Reference is now made to FIG. 4 to more fully appreciate the failure mechanism resulting from snapback. When the drain voltage reaches V.sub.t1, the device triggers into snapback. With sufficient current flowing in the snapback region, the device triggers into second breakdown (i.e., thermal runaway and current instability). Current flow through the snapback region is substantially uniform, and does not generally cause device failure. However, current flow indicated in the second breakdown region may form a "current filament"; this nonuniform current flow causes the device to fail, with a source-to-drain short. In the context of a multi-finger architecture, the failure threshold of the device is determined by the number of "fingers" (i.e., individual n-channel FETs 28.sub.1, 28.sub.2, . . . 28.sub.N) that are turned-on and conducting in the snapback region before second breakdown occurs. That is, the greater the number of individual transistors carrying the ESD charge, the lower the likelihood of device failure due to current damage.
One approach taken in the art for remedying the above-identified second breakdown device failure mode calls for disposing a polysilicon or silicide resistor between the I/O pad 16 and the drain region of n-channel pulldown device 28. Although this approach was found to be satisfactory in terms of increasing the ESD failure threshold, as compared to a design without a resistor, the approach had the significant disadvantage in that such a resistor could not be integrated into a structure, such as the structure shown in FIG. 2, which merges the drain of n-channel pulldown FET 28, and the cathode of diode D.sub.1. This approach is thus not very compact.
Another disadvantage in the prior art as shown in FIG. 1 and 2, is that it requires the power supply bus V.sub.SSI to be connected to diode D.sub.1. Therefore, V.sub.SSI must be routed to the I/O cell. Further, the metal width of the V.sub.SSI bus must be large enough to carry the current during an ESD event without fusing open. For example, the design rules for one fabrication process dictates that the metal bus width must be 15 .mu.m. The requirement that the V.sub.SSI power supply bus be routed to the I/O cell, with a significant width, can lead to a significant increase in the cell area, or, the die area.
Accordingly, there is a need to provide an improved ESD protection circuit suitable for use in an integrated circuit, that minimizes or eliminates one or more of the problems as set forth above.